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» A Functional DBPL Revealing High Level Optimizations
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ICCD
2008
IEEE
146views Hardware» more  ICCD 2008»
16 years 22 days ago
Chip level thermal profile estimation using on-chip temperature sensors
—This paper addresses the problem of chip level thermal profile estimation using runtime temperature sensor readings. We address the challenges of a) availability of only a few t...
Yufu Zhang, Ankur Srivastava, Mohamed M. Zahran
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
15 years 8 months ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
148
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VLSID
2002
IEEE
116views VLSI» more  VLSID 2002»
16 years 4 months ago
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
Kuo-Hsing Cheng, Shun-Wen Cheng
JMLR
2012
13 years 6 months ago
Random Search for Hyper-Parameter Optimization
Grid search and manual search are the most widely used strategies for hyper-parameter optimization. This paper shows empirically and theoretically that randomly chosen trials are ...
James Bergstra, Yoshua Bengio
BIOCOMP
2008
15 years 5 months ago
Prediction of Protein Function Using Graph Container and Message Passing
We introduce a novel parameter called container flux, which is used to measure the information sharing capacity between two distinct nodes in a graph. Other useful information, bot...
Hongbo Zhou, Qiang Shawn Cheng, Mehdi Zargham