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ISCA
2009
IEEE
239views Hardware» more  ISCA 2009»
14 years 5 months ago
Scalable high performance main memory system using phase-change memory technology
The memory subsystem accounts for a significant cost and power budget of a computer system. Current DRAM-based main memory systems are starting to hit the power and cost limit. A...
Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Ju...
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 5 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
MICRO
2009
IEEE
133views Hardware» more  MICRO 2009»
14 years 5 months ago
A tagless coherence directory
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin...
MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
14 years 5 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
WDAG
2009
Springer
147views Algorithms» more  WDAG 2009»
14 years 5 months ago
Compact Routing in Power-Law Graphs
Abstract. We adapt the compact routing scheme by Thorup and Zwick to optimize it for power-law graphs. We analyze our adapted routing scheme based on the theory of unweighted rando...
Wei Chen, Christian Sommer 0002, Shang-Hua Teng, Y...
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