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» A Gradually Proceeded Software Architecture Design Process
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CODES
2009
IEEE
15 years 9 months ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
ICES
2003
Springer
165views Hardware» more  ICES 2003»
15 years 7 months ago
Speeding up Hardware Evolution: A Coprocessor for Evolutionary Algorithms
This paper proposes a coprocessor architecture to speed up hardware evolution. It is designed to be implemented in an FPGA with an integrated microprocessor core. The coprocessor r...
Tillmann Schmitz, Steffen G. Hohmann, Karlheinz Me...
143
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FDL
2003
IEEE
15 years 7 months ago
Object-Oriented ASIP Design and Synthesis
SystemC-Plus from the ODETTE project provides the ability to simulate and synthesise object-oriented specifications into hardware. The current ODETTE compiler translates each obj...
Maziar Goudarzi, Shaahin Hessabi, Alan Mycroft
SIGSOFT
2010
ACM
15 years 10 days ago
Finding latent performance bugs in systems implementations
Robust distributed systems commonly employ high-level recovery mechanisms enabling the system to recover from a wide variety of problematic environmental conditions such as node f...
Charles Edwin Killian, Karthik Nagaraj, Salman Per...
DAC
2001
ACM
16 years 3 months ago
MetaCores: Design and Optimization Techniques
Currently, hardware intellectual property (IP) is delivered at vels of abstraction: hard, firm, and soft. In order to further enhance performance, efficiency, and flexibility of I...
Seapahn Meguerdichian, Farinaz Koushanfar, Advait ...