21 search results - page 4 / 5 » A Graph-Theoretic Approach to Clock Skew Optimization |
TVLSI
2010
13 years 2 months ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
ICCAD
1997
IEEE
13 years 11 months ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
ISPD
2003
ACM
14 years 24 days ago
2003
ACM
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
ICCAD
2007
IEEE
14 years 4 months ago
2007
IEEE
Abstract— Rotary traveling-wave oscillator (RTWO) is a recently proposed transmission-line approach for multi-gigahertz rate clock generation. RTWO has the characteristics of bot...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
The concept of improving the timing behavior of a circuit by relocating flip-flops is called retiming and was first presented by Leiserson and Saxe. The ASTRA algorithm propose...