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» A Hardware Algorithm for Integer Division
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DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 3 months ago
Scalable compile-time scheduler for multi-core architectures
As the number of cores continues to grow in both digital signal and general purpose processors, tools which perform automatic scheduling from model-based designs are of increasing...
Maxime Pelcat, Pierrick Menuet, Slaheddine Aridhi,...
SBACPAD
2007
IEEE
128views Hardware» more  SBACPAD 2007»
14 years 2 months ago
Node Level Primitives for Parallel Exact Inference
We present node level primitives for parallel exact inference on an arbitrary Bayesian network. We explore the probability representation on each node of Bayesian networks and eac...
Yinglong Xia, Viktor K. Prasanna
ICCAD
2005
IEEE
160views Hardware» more  ICCAD 2005»
14 years 5 months ago
Equivalence verification of polynomial datapaths with fixed-size bit-vectors using finite ring algebra
— This paper addresses the problem of equivalence verification of RTL descriptions. The focus is on datapathoriented designs that implement polynomial computations over fixed-s...
Namrata Shekhar, Priyank Kalla, Florian Enescu, Si...
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
14 years 2 months ago
Design closure driven delay relaxation based on convex cost network flow
Design closure becomes hard to achieve at physical layout stage due to the emergence of long global interconnects. Consequently, interconnect planning needs to be integrated in hi...
Chuan Lin, Aiguo Xie, Hai Zhou
ICCAD
1997
IEEE
101views Hardware» more  ICCAD 1997»
14 years 25 days ago
Minimum area retiming with equivalent initial states
Traditional minimum area retiming algorithms attempt to achieve their prescribed objective with no regard to maintaining the initial state of the system. This issue is important f...
Naresh Maheshwari, Sachin S. Sapatnekar