Sciweavers

199 search results - page 30 / 40
» A Hardware Algorithm for Integer Division
Sort
View
ARITH
2007
IEEE
14 years 2 months ago
P6 Binary Floating-Point Unit
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
Son Dao Trong, Martin S. Schmookler, Eric M. Schwa...
MEMOCODE
2007
IEEE
14 years 2 months ago
From WiFi to WiMAX: Techniques for High-Level IP Reuse across Different OFDM Protocols
Orthogonal Frequency-Division Multiplexing (OFDM) has become the preferred modulation scheme for both broadband and high bitrate digital wireless protocols because of its spectral...
Man Cheuk Ng, Muralidaran Vijayaraghavan, Nirav Da...
CG
2008
Springer
13 years 8 months ago
Barycentric coordinates computation in homogeneous coordinates
Homogeneous coordinates are often used in computer graphics and computer vision applications especially for the representation of geometric transformations. The homogeneous coordi...
Václav Skala
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
14 years 3 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
ICCAD
2003
IEEE
129views Hardware» more  ICCAD 2003»
14 years 1 months ago
Performance Optimization of Latency Insensitive Systems Through Buffer Queue Sizing of Communication Channels
This paper proposes for latency insensitive systems a performance optimization technique called channel buffer queue sizing, which is performed after relay station insertion in th...
Ruibing Lu, Cheng-Kok Koh