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» A Hardware Algorithm for Integer Division
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ICCAD
2007
IEEE
234views Hardware» more  ICCAD 2007»
14 years 13 days ago
Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors
Abstract: Polynomial computations over fixed-size bitvectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositi...
Sivaram Gopalakrishnan, Priyank Kalla, M. Brandon ...
ICCAD
2009
IEEE
154views Hardware» more  ICCAD 2009»
13 years 6 months ago
Pad assignment for die-stacking System-in-Package design
Wire bonding is the most popular method to connect signals between dies in System-in-Package (SiP) design nowadays. Pad assignment, which assigns inter-die signals to die pads so ...
Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang
ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
14 years 2 months ago
Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
Weiping Shi, Zhuo Li, Charles J. Alpert
STOC
2009
ACM
168views Algorithms» more  STOC 2009»
14 years 9 months ago
Fault-tolerant spanners for general graphs
The paper concerns graph spanners that are resistant to vertex or edge failures. Given a weighted undirected n-vertex graph G = (V, E) and an integer k 1, the subgraph H = (V, E ...
Shiri Chechik, Michael Langberg, David Peleg, Liam...
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
14 years 5 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim