1998 search results - page 72 / 400 » A Hardware Implementation of PRAM and Its Performance Evalua... |
HPCA
1998
IEEE
14 years 1 months ago
1998
IEEE
A key challenge in achieving high performance on software DSM systems is overcoming their relatively large communication latencies. In this paper, we consider two techniques which...
ASPLOS
1991
ACM
14 years 20 days ago
1991
ACM
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
IPPS
1998
IEEE
14 years 1 months ago
1998
IEEE
Abstract. Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an archit...
ISCAS
2007
IEEE
14 years 3 months ago
2007
IEEE
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
ISCA
2011
IEEE
13 years 25 days ago
2011
IEEE
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...