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DAC
2008
ACM
14 years 8 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
SAMOS
2004
Springer
14 years 26 days ago
High-Level Energy Estimation for ARM-Based SOCs
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
Dan Crisu, Sorin Cotofana, Stamatis Vassiliadis, P...
ISQED
2006
IEEE
106views Hardware» more  ISQED 2006»
14 years 1 months ago
Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration
We propose an accurate architecture-level power estimation method for SRAM memories. This hybrid method is composed of an analytical part for dynamic power estimation and a circui...
Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-...
ECIS
2001
13 years 9 months ago
Building an Enterprise Architecture for Public Administration: A High Level Data Model for Strategic Planning
This paper describes the construction of a generic data model for strategic planning in Public Administration (PA). This model is presented at two distinct levels corresponding to...
Konstantinos A. Tarabanis, Vassilios Peristeras, G...
ISN
1994
Springer
136views Communications» more  ISN 1994»
13 years 11 months ago
High-Level Access APIs in the OSIMIS TMN Platform: Harnessing and Hiding
There is a common unjustified belief that OSI management technology, despite being very powerful, is difficult to implement because of the complexity of the underlying service/prot...
George Pavlou, Thurain Tin, Andy Carr