Sciweavers

110 search results - page 11 / 22
» A Highly-Configurable Cache Architecture for Embedded System...
Sort
View
DAC
2003
ACM
14 years 9 months ago
Accurate timing analysis by modeling caches, speculation and their interaction
Schedulability analysis of real-time embedded systems requires worst case timing guarantees of embedded software performance. This involves not only language level program analysi...
Xianfeng Li, Tulika Mitra, Abhik Roychoudhury
DATE
2002
IEEE
104views Hardware» more  DATE 2002»
14 years 1 months ago
Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors
In this paper, we suggest hardware-assisted data compression as a tool for reducing energy consumption of core-based embedded systems. We propose a novel and e cient architecture ...
Luca Benini, Davide Bruni, Alberto Macii, Enrico M...
MIDDLEWARE
2004
Springer
14 years 2 months ago
On adaptable middleware product lines
Middleware helps to manage the complexity and heterogeneity inherent in distributed systems. Traditional middleware has a monolithic architecture, which makes it difficult to adap...
Wasif Gilani, Nabeel Hasan Naqvi, Olaf Spinczyk
ISORC
2009
IEEE
14 years 3 months ago
Thread-Local Scope Caching for Real-time Java
There is increasing convergence between the fields of parallel and embedded computing. The demand for more functionality in embedded devices means that complex multicore architec...
Andy J. Wellings, Martin Schoeberl
RTAS
2005
IEEE
14 years 2 months ago
Bounding Worst-Case Data Cache Behavior by Analytically Deriving Cache Reference Patterns
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
Harini Ramaprasad, Frank Mueller