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DAC
1997
ACM
15 years 7 months ago
A Hybrid Algorithm for Test Point Selection for Scan-Based BIST
Huan-Chih Tsai, Kwang-Ting Cheng, Chih-Jen Lin, Su...
VLSID
2002
IEEE
82views VLSI» more  VLSID 2002»
16 years 3 months ago
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST
Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Raj...
DFT
2009
IEEE
106views VLSI» more  DFT 2009»
15 years 10 months ago
Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points
Recently, a new test point insertion method for pseudo-random built-in self-test (BIST) was proposed in [Yang 09] which tries to use functional flip-flops to drive control test po...
Joon-Sung Yang, Benoit Nadeau-Dostie, Nur A. Touba
ET
2002
67views more  ET 2002»
15 years 3 months ago
On-the-Fly Reseeding: A New Reseeding Technique for Test-Per-Clock BIST
In this paper we present a new reseeding technique for test-per-clock test pattern generation suitable for at-speed testing of circuits with random-pattern resistant faults. Our te...
Emmanouil Kalligeros, Xrysovalantis Kavousianos, D...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
15 years 7 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...