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VTS
2006
IEEE
101views Hardware» more  VTS 2006»
14 years 1 months ago
Design Optimization for Robustness to Single Event Upsets
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
DAC
1996
ACM
13 years 11 months ago
POSE: Power Optimization and Synthesis Environment
Recent trends in the semiconductor industry have resulted in an increasing demand for low power circuits. POSE is a step in providing the EDA community and academia with an enviro...
Sasan Iman, Massoud Pedram
GECCO
2005
Springer
128views Optimization» more  GECCO 2005»
14 years 1 months ago
Fractional dynamic fitness functions for GA-based circuit design
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...
Cecília Reis, José António Te...
DELTA
2006
IEEE
13 years 11 months ago
Synthesis of Nanoelectronic Circuits on Delay-Insensitive Cellular Arrays
The difficulties of designing nanoscale circuits include the need for regular circuit structure and controlling the timing requirements. A cellular array has highly regular struct...
Jia Di, Dilip P. Vasudevan
EUROGP
2004
Springer
135views Optimization» more  EUROGP 2004»
14 years 26 days ago
Reusing Code in Genetic Programming
Abstract. In this paper we propose an approach to Genetic Programming based on code reuse and we test it in the design of combinational logic circuits at the gate-level. The circui...
Edgar Galván López, Riccardo Poli, C...