1410 search results - page 158 / 282 » A Logic for Virtual Memory |
154
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ICTAC
2010
Springer
15 years 2 months ago
2010
Springer
We consider software verification of imperative programs by theorem proving in higher-order separation logic. Of particular interest are the difficulties of encoding and reasoning ...
131
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DAC
2003
ACM
16 years 5 months ago
2003
ACM
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...
107
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ICCAD
2007
IEEE
16 years 1 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...
137
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DATE
2009
IEEE
15 years 11 months ago
2009
IEEE
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
105
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DATE
2007
IEEE
15 years 11 months ago
2007
IEEE
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...