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MICRO
2010
IEEE
172views Hardware» more  MICRO 2010»
15 years 2 months ago
Architectural Support for Fair Reader-Writer Locking
Abstract--Many shared-memory parallel systems use lockbased synchronization mechanisms to provide mutual exclusion or reader-writer access to memory locations. Software locks are i...
Enrique Vallejo, Ramón Beivide, Adriá...
ARC
2009
Springer
102views Hardware» more  ARC 2009»
15 years 11 months ago
A Parallel Branching Program Machine for Emulation of Sequential Circuits
The parallel branching program machine (PBM128) consists of 128 branching program machines (BMs) and a programmable interconnection. To represent logic functions on BMs, we use qua...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura,...
ISSS
2002
IEEE
142views Hardware» more  ISSS 2002»
15 years 9 months ago
Energy/Power Estimation of Regular Processor Arrays
We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for i...
Sanjay V. Rajopadhye, Steven Derrien
ASPDAC
2006
ACM
109views Hardware» more  ASPDAC 2006»
15 years 8 months ago
Hardware debugging method based on signal transitions and transactions
- This paper proposes a hardware design debugging method, Transition and Transaction Tracer (TTT), which probes and records the signals of interest for a long time, hours, days, or...
Nobuyuki Ohba, Kohji Takano
VVEIS
2008
15 years 6 months ago
An Executable Semantics of Object-oriented Models for Simulation and Theorem Proving
This paper presents an executable semantics of OO models. We made it possible to conduct both simulation and theorem proving on the semantics by implementing its underlying heap me...
Kenro Yatake, Takuya Katayama