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» A Logical Viewpoint on Architectures
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ISQED
2007
IEEE
124views Hardware» more  ISQED 2007»
16 years 8 days ago
Multi-Dimensional Circuit and Micro-Architecture Level Optimization
This paper studies multi-dimensional optimization at both circuit and micro-architecture levels. By formulating and solving the optimization problem with conflicting design objec...
Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonock...
DATE
2005
IEEE
110views Hardware» more  DATE 2005»
15 years 11 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
ISSS
1998
IEEE
96views Hardware» more  ISSS 1998»
15 years 10 months ago
Fine Grain Incremental Rescheduling Via Architectural Retiming
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
Soha Hassoun
WSC
1998
15 years 7 months ago
Architecture for a Non-deterministic Simulation Machine
Causality constraints of random discrete simulation make parallel and distributed processing difficult. Methods of applying reconfigurable logic to implement and accelerate simula...
Marc Bumble, Lee D. Coraor
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
15 years 11 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose