49 search results - page 1 / 10 » A Low Power Charge-Recycling CMOS Clock Buffer |
GLVLSI
1999
IEEE
14 years 3 months ago
1999
IEEE
ISCAS
2002
IEEE
14 years 3 months ago
2002
IEEE
The main result of this paper is the development of a low depth carry lookahead addition technique based on threshold logic. Two such adders are designed using the recently propos...
DAC
2006
ACM
14 years 11 months ago
2006
ACM
Designing an energy efficient power gating structure is an important and challenging task in Multi-Threshold CMOS (MTCMOS) circuit design. In order to achieve a very low power des...
ASPDAC
2008
ACM
14 years 25 days ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
ISCAS
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract—Design guidelines for resonant H-tree clock distribution networks are presented in this paper. A distributed model of a two-level resonant H-tree structure is described,...