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» A Low-Power Cache Design for CalmRISCTM-Based Systems
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CODES
2000
IEEE
15 years 8 months ago
Parameterized system design
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To b...
Tony Givargis, Frank Vahid
IPCCC
2006
IEEE
15 years 9 months ago
OS-aware tuning: improving instruction cache energy efficiency on system workloads
Low power has been considered as an important issue in instruction cache (I-cache) designs. Several studies have shown that the I-cache can be tuned to reduce power. These techniq...
Tao Li, Lizy K. John
172
Voted
ISLPED
2010
ACM
128views Hardware» more  ISLPED 2010»
15 years 1 months ago
Rank-aware cache replacement and write buffering to improve DRAM energy efficiency
DRAM power and energy efficiency considerations are becoming increasingly important for low-power and mobile systems. Using lower power modes provided by commodity DRAM chips redu...
Ahmed M. Amin, Zeshan Chishti
DAC
1998
ACM
16 years 4 months ago
Power Optimization of Variable Voltage Core-Based Systems
The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by domin...
Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkon...
121
Voted
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
15 years 7 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...