This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
We present a methodology for the design and analysis of power grids in the PowerPC™ microprocessors. The methodology covers the need for power grid analysis across all stages of...
Abhijit Dharchoudhury, Rajendran Panda, David Blaa...
Background: In individually dye-balanced microarray designs, each biological sample is hybridized on two different slides, once with Cy3 and once with Cy5. While this strategy ens...
The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account sin...
Marco Caldari, Massimo Conti, Massimo Coppola, Pao...
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...