383 search results - page 29 / 77 » A Methodology for High Level Power Estimation and Exploratio... |
DAC
2005
ACM
14 years 8 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
DCC
2008
IEEE
13 years 9 months ago
2008
IEEE
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
ISVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
The behavior of many algorithms is heavily determined by the input data. Furthermore, this often means that multiple and completely different execution paths can be followed, also...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...