383 search results - page 30 / 77 » A Methodology for High Level Power Estimation and Exploratio... |
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and method...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power mo...
TCAD
2002
13 years 7 months ago
2002
Specialized clustered very large instruction word (VLIW) processors combined with effective compilation techniques enable aggressive exploitation of the high instruction-level para...
FPL
2009
Springer
14 years 11 days ago
2009
Springer
This paper presents a methodology for estimating and optimising FPGA routing fabrics using high-level modelling and convex optimisation techniques. Experimental methods for explor...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...