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ISCAPDCS
2007
13 years 9 months ago
Architectural requirements of parallel computational biology applications with explicit instruction level parallelism
—The tremendous growth in the information culture, efficient digital searches are needed to extract and identify information from huge data. The notion that evolution in silicon ...
Naeem Zafar Azeemi
ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
14 years 1 months ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh
ISPD
1999
ACM
128views Hardware» more  ISPD 1999»
14 years 2 days ago
Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
There is an increasing need in modern VLSI designs for circuits implemented in high-performance logic families such as Cascode Voltage Switch Logic, Pass Transistor Logic, and dom...
Michael A. Riepe, Karem A. Sakallah
ICASSP
2011
IEEE
12 years 11 months ago
Power allocation for orthogonal AF relay systems with outage-based QOS constraints
We consider the problem of minimizing the cost of the power required to achieve a specified level of quality-of-service (QoS) on a point-to-point link that may be assisted by an ...
Rooholah Hasanizadeh, Timothy N. Davidson
CLUSTER
2007
IEEE
13 years 11 months ago
Identifying energy-efficient concurrency levels using machine learning
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...
Matthew Curtis-Maury, Karan Singh, Sally A. McKee,...