109 search results - page 20 / 22 » A Methodology for Large-Scale Hardware Verification |
DAC
2005
ACM
14 years 10 months ago
2005
ACM
Recent study shows that the existing first order canonical timing model is not sufficient to represent the dependency of the gate delay on the variation sources when processing an...
BMCBI
2005
13 years 9 months ago
2005
Background: Expressed Sequence Tags (ESTs) are short and error-prone DNA sequences generated from the 5' and 3' ends of randomly selected cDNA clones. They provide an im...
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
Constraining and input biasing are frequently used techniques in functional verification methodologies based on randomized simulation generation. Constraints confine the simulatio...
DATE
2006
IEEE
14 years 3 months ago
2006
IEEE
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
SBCCI
2005
ACM
14 years 3 months ago
2005
ACM
Higher integration densities, smaller feature lengths, and other technology advances, as well as architectural evolution, have made microprocessor cores exceptionally complex. Cur...