43 search results - page 4 / 9 » A Mixed Circuit and System Level Simulation Technique of Col... |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
Majority of existing works on system level power estimation have focused on the processor, while there are very few that address power consumption of peripherals in a SoC. With th...
DFT
2007
IEEE
14 years 1 months ago
2007
IEEE
Decreasing feature sizes have led to an increased vulnerability of random logic to soft errors. A particle strike may cause a glitch or single event transient (SET) at the output ...
ISQED
2002
IEEE
14 years 12 days ago
2002
IEEE
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—This paper introduces a technique to measure and adjust the relative phase of on-chip high speed digital signals using a random sampling technique of inferential statistics. The...
ASYNC
2000
IEEE
13 years 12 months ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...