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DAC
2006
ACM
14 years 2 months ago
SystemC transaction level models and RTL verification
This paper describes how systems companies are adopting SystemC transaction level models for system on chip design and verification, and how these transaction level models are bei...
Stuart Swan
ICECCS
2005
IEEE
65views Hardware» more  ICECCS 2005»
14 years 2 months ago
Principles, Standards and Tools for Model Engineering
We take here a broad view of model engineering as encompassing different approaches such as the OMG MDA™ proposal [9], the Microsoft Software Factories view [5], and many others...
Jean Bézivin, Frédéric Jouaul...
DATE
2009
IEEE
151views Hardware» more  DATE 2009»
14 years 3 months ago
pTest: An adaptive testing tool for concurrent software on embedded multicore processors
—More and more processor manufacturers have launched embedded multicore processors for consumer electronics products because such processors provide high performance and low powe...
Shou-Wei Chang, Kun-Yuan Hsieh, Jenq Kuen Lee
ATS
2003
IEEE
131views Hardware» more  ATS 2003»
14 years 1 months ago
Software-Based Delay Fault Testing of Processor Cores
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hi...
ACSAC
2003
IEEE
14 years 1 months ago
MLS-PCA: A High Assurance Security Architecture for Future Avionics
1 DOD Joint Vision 2020 (JV2020) is the integrated multi-service planning document for conduct among coalition forces of future warfare. It requires the confluence of a number of k...
Clark Weissman