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CODES
2003
IEEE
14 years 21 days ago
Schedule-aware performance estimation of communication architecture for efficient design space exploration
In this paper, we are concerned about the performance estimation of bus-based architectures assuming that the task partitioning on the processing components is already determined....
Sungchan Kim, Chaeseok Im, Soonhoi Ha
FPL
2007
Springer
190views Hardware» more  FPL 2007»
14 years 1 months ago
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems
Today’s heterogeneous embedded systems combine components from different domains, such as software, analogue hardware and digital hardware. The design and implementation of thes...
Andreas Herrholz, Frank Oppenheimer, Philipp A. Ha...
GRAPHITE
2003
ACM
14 years 20 days ago
Real-time image based lighting in software using HDR panoramas
We present a system allowing real-time image based lighting based on HDR panoramic images. The system performs time-consuming diffuse light calculations in a preprocessing step, w...
Jonas Unger, Magnus Wrenninge, Mark Ollila
FPL
2003
Springer
81views Hardware» more  FPL 2003»
14 years 19 days ago
Software Decelerators
This paper introduces the notion of a software decelerator, to be used in logic-centric system architectures. Functions are offloaded from logic to a processor, accepting a speed ...
Eric Keller, Gordon J. Brebner, Philip James-Roxby
IEEEMM
2002
134views more  IEEEMM 2002»
13 years 7 months ago
A Middleware Architecture for Open and Interoperable GISs
an abstract model for information sharing and integration and use it to develop an architecture for building open, component-based, interoperable systems. A geographic information ...
Steven H. Wong, Steven L. Swartz, Dilip Sarkar