389 search results - page 4 / 78 » A Model for the Coanalysis of Hardware and Software Architec... |
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
This paper presents a task-centric memory model for 1000-core compute accelerators. Visual computing applications are emerging as an important class of workloads that can exploit ...
ICECCS
2005
IEEE
14 years 28 days ago
2005
IEEE
Security design at architecture level is critical to achieve high assurance software systems. However, most security design techniques for software architectures were in ad hoc fa...
DSD
2011
IEEE
12 years 7 months ago
2011
IEEE
Abstract—We present a new low-level interfacing scheme for connecting custom accelerators to processors that tolerates latencies that usually occur when accessing hardware accele...
DATE
2003
IEEE
14 years 19 days ago
2003
IEEE
This paper describes the design considerations of and preliminary conclusions drawn from an ongoing project dealing with the design of a software architecture for a family of so-c...
DATE
2005
IEEE
14 years 29 days ago
2005
IEEE
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...