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ASPLOS
1996
ACM
14 years 20 days ago
Synchronization and Communication in the T3E Multiprocessor
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...
Steven L. Scott
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
14 years 1 months ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
ICIP
1999
IEEE
14 years 10 months ago
Architecture of Embedded Video Processing in a Multimedia Chip-Set
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
Egbert G. T. Jaspers, Peter H. N. de With
IPPS
1998
IEEE
14 years 23 days ago
BIP: A New Protocol Designed for High Performance Networking on Myrinet
Abstract. High speed networks are now providing incredible performances. Software evolution is slow and the old protocol stacks are no longer adequate for these kind of communicati...
Loïc Prylli, Bernard Tourancheau
3DIC
2009
IEEE
169views Hardware» more  3DIC 2009»
14 years 1 months ago
3-D memory organization and performance analysis for multi-processor network-on-chip architecture
Several forms of processor memory organizations have been in use to optimally access off-chip memory systems mainly the Hard disk drives (HDD). Recent trends show that the solid s...
Awet Yemane Weldezion, Zhonghai Lu, Roshan Weerase...