3629 search results - page 11 / 726 » A Network Memory Architecture Model and Performance Analysis |
ICDE
2006
IEEE
14 years 9 months ago
2006
IEEE
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
JUCS
2000
13 years 7 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
This paper addresses the problem of efficient and accurate performance analysis to drive the exploration and design of bus-based System-on-Chip (SOC) communication architectures. ...
FOCI
2007
IEEE
14 years 2 months ago
2007
IEEE
Recent progress in genomics and proteomics makes it possible to understand the biological networks at the systems level. We aim to develop computational models of learning and memo...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...