465 search results - page 9 / 93 » A New Approach for Low Power Scan Testing |
VTS
1997
IEEE
13 years 11 months ago
1997
IEEE
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
VTS
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
IPCCC
2006
IEEE
14 years 1 months ago
2006
IEEE
Considerable research has been done on detecting and blocking portscan activities that are typically conducted by infected hosts to discover other vulnerable hosts. However, the f...
RECOMB
2005
Springer
14 years 7 months ago
2005
Springer
Abstract. Asymmetric functional divergence of paralogues is a key aspect of the traditional model of evolution following duplication. If one gene continues to perform the ancestral...
EVOW
1999
Springer
13 years 11 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...