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» A New Method for Design of Robust Digital Circuits
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VTS
2007
IEEE
129views Hardware» more  VTS 2007»
14 years 3 months ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
CHI
1996
ACM
14 years 1 months ago
Structuring Information with Mental Models: A Tour of Boston
We present a new systematic method of structuring information using mental models. This method can be used both to evaluate the efficiency of an information structure and to build...
Ishantha Lokuge, Stephen A. Gilbert, Whitman Richa...
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 3 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
GLVLSI
2002
IEEE
109views VLSI» more  GLVLSI 2002»
14 years 2 months ago
Minimizing resources in a repeating schedule for a split-node data-flow graph
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha
ASPDAC
2008
ACM
200views Hardware» more  ASPDAC 2008»
13 years 11 months ago
Non-Gaussian statistical timing analysis using second-order polynomial fitting
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Lerong Cheng, Jinjun Xiong, Lei He