945 search results - page 9 / 189 » A New Method for Design of Robust Digital Circuits |
IOLTS
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity p...
MEMOCODE
2007
IEEE
14 years 1 months ago
2007
IEEE
—With the arrival of nanometer technologies wire delays are no longer negligible with respect to gate delays, and timing-closure becomes a major challenge to System-on-Chip desig...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
In this paper, we propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is form...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synch...