Sciweavers

371 search results - page 6 / 75
» A New Method for Interoperability Test Generation
Sort
View
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
14 years 11 days ago
A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
Sooryong Lee, Brad Cobb, Jennifer Dworak, Michael ...
FOSAD
2005
Springer
14 years 28 days ago
Formal Methods for Smartcard Security
Smartcards are trusted personal devices designed to store and process confidential data, and to act as secure tokens for providing access to applications and services. Smartcards ...
Gilles Barthe, Guillaume Dufay
ICCAD
1998
IEEE
116views Hardware» more  ICCAD 1998»
13 years 11 months ago
On primitive fault test generation in non-scan sequential circuits
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...
Ramesh C. Tekumalla, Premachandran R. Menon
MTDT
2003
IEEE
124views Hardware» more  MTDT 2003»
14 years 21 days ago
Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes
Abstract: The high complexity of the faulty behavior observed in DRAMs is caused primarily by the presence of internal floating nodes in defective DRAMs. This paper describes a ne...
Zaid Al-Ars, A. J. van de Goor
CADE
2006
Springer
14 years 7 months ago
Blocking and Other Enhancements for Bottom-Up Model Generation Methods
In this paper we introduce several new improvements to the bottom-up model generation (BUMG) paradigm. Our techniques are based on non-trivial transformations of first-order probl...
Peter Baumgartner, Renate A. Schmidt