73 search results - page 3 / 15 » A New Pipelined Array Architecture for Signed Multiplication |
ISCAS
1993
IEEE
13 years 11 months ago
1993
IEEE
A fully pipelined systolic array structure for multidimensional adaptive filtering is proposed. It utilizes the wellknown McClellan Transformation (MT) to reduce the total number ...
ARITH
2007
IEEE
14 years 1 months ago
2007
IEEE
The floating-point multiply-add fused (MAF) unit sets a new trend in the processor design to speed up floatingpoint performance in scientific and multimedia applications. This ...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
HCW
2000
IEEE
13 years 11 months ago
2000
IEEE
In a serverless cluster of PCs or workstations, the cluster must allow remote file accesses or parallel I/O directly performed over disks distributed to all client nodes. We intro...
FCCM
2008
IEEE
14 years 1 months ago
2008
IEEE
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...