935 search results - page 4 / 187 » A New Statistical Optimization Algorithm for Gate Sizing |
TSP
2008
13 years 7 months ago
2008
A new framework for designing robust adaptive filters is introduced. It is based on the optimization of a certain cost function subject to a time-dependent constraint on the norm o...
ISCAS
2011
IEEE
12 years 11 months ago
2011
IEEE
—A unified optimization framework is presented for simultaneous gate sizing and placement. These processes are unified using Lagrangian multipliers, which synchronize the efforts...
JCO
2011
13 years 2 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...