522 search results - page 11 / 105 » A Note on Designing Logical Circuits Using SAT |
ISMVL
2008
IEEE
14 years 1 months ago
2008
IEEE
Abstract—This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a ...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Circuit fabrics composed of highly regular structures, called logic bricks, have been described recently for improving yield. An automated logic brick design flow based on a SAT ...
ISMVL
2010
IEEE
14 years 4 days ago
2010
IEEE
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
DAC
2005
ACM
14 years 8 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...
ET
2010
13 years 5 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...