522 search results - page 13 / 105 » A Note on Designing Logical Circuits Using SAT |
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
ASPDAC
2004
ACM
14 years 22 days ago
2004
ACM
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
CSREAESA
2003
13 years 8 months ago
2003
In this paper we address the problem of minimization of power consumption in combinational circuits by minimizing the number of switching transitions at the output nodes of each g...
VLSID
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract— This paper introduces a fuzzy logic based guidance architecture to a graph grammar framework for automated design of analog circuits. The grammar generates circuit topo...
TCAD
2002
13 years 7 months ago
2002
Many tasks in CAD, such as equivalence checking, property checking, logic synthesis, and false paths analysis require efficient Boolean reasoning for problems derived from circuits...