522 search results - page 26 / 105 » A Note on Designing Logical Circuits Using SAT |
CSREAESA
2003
13 years 8 months ago
2003
Most so-called “adiabatic” digital logic circuit families reported in the low-power design literature are actually not truly adiabatic, in that they do not satisfy the general...
DAC
2004
ACM
14 years 23 days ago
2004
ACM
The Pentium® 4 processor architecture uses a 2x frequency core clock[1] to implement low latency integer ops. Low Voltage Swing logic circuits implemented in 90nm technology[2] m...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Threshold logic is gaining prominence as an alternative to Boolean logic. The main reason for this trend is the availability of devices that implement these circuits efficiently (...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
In many designs, the worst-case-delay path may never be exercised or may be exercised infrequently. For those designs, a strategy of optimizing a circuit for the worst-case condit...