522 search results - page 32 / 105 » A Note on Designing Logical Circuits Using SAT |
ISCAS
1999
IEEE
13 years 11 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
DDECS
2009
IEEE
14 years 2 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
—A problem in technology mapping is that the quality of the final implementation depends significantly on the initially provided circuit structure. This problem is critical, es...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
Abstract Althoughtremendousadvanceshave been accomplished in logic synthesis in the past two decades, in some cases logic synthesis still cannot attain the improvements possible by...
GLVLSI
2009
IEEE
13 years 10 months ago
2009
IEEE
In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into async...