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» A Note on Designing Logical Circuits Using SAT
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DATE
2000
IEEE
142views Hardware» more  DATE 2000»
13 years 12 months ago
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
Traditional FPGA design flows have treated logic synthesis and physical design as separate steps. With the recent advances in technology, the lack of information on the physical ...
Balakrishna Kumthekar, Fabio Somenzi
DAC
1998
ACM
14 years 8 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
CASES
2010
ACM
13 years 5 months ago
Implementing virtual secure circuit using a custom-instruction approach
Although cryptographic algorithms are designed to resist at least thousands of years of cryptoanalysis, implementing them with either software or hardware usually leaks additional...
Zhimin Chen, Ambuj Sinha, Patrick Schaumont
DATE
2009
IEEE
122views Hardware» more  DATE 2009»
14 years 2 months ago
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues
—Nonvolatile logic-in-memory architecture, where nonvolatile memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced i...
Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuy...
GLVLSI
2003
IEEE
134views VLSI» more  GLVLSI 2003»
14 years 21 days ago
Modeling QCA for area minimization in logic synthesis
Concerned by the wall that Moore’s Law is expected to hit in the next decade, the integrated circuit community is turning to emerging nanotechnologies for continued device impro...
Nadine Gergel, Shana Craft, John Lach