522 search results - page 71 / 105 » A Note on Designing Logical Circuits Using SAT |
GLVLSI
2003
IEEE
14 years 1 months ago
2003
IEEE
A new split accumulator architecture to be used in direct digital frequency synthesizers (DDFS) systems is presented. This new design eliminates the need of adders on the section ...
DAC
2010
ACM
13 years 12 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
PODS
2006
ACM
14 years 8 months ago
2006
ACM
Given that most elementary problems in database design are NP-hard, the currently used database design algorithms produce suboptimal results. For example, the current 3NF decompos...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...