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» A Note on Designing Logical Circuits Using SAT
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ICCAD
1996
IEEE
92views Hardware» more  ICCAD 1996»
14 years 4 days ago
Generation of BDDs from hardware algorithm descriptions
We propose a new method for generating BDDs from hardware algorithm descriptions written in a programming language. Our system can deal with control structures, such as conditiona...
Shin-ichi Minato
HT
1987
ACM
13 years 11 months ago
Exploring Representation Problems Using Hypertext
Hypertext is a technology well-suited to exploring different kinds of representational problems. It can be used first as an informal mechanism to describe the attributes of object...
Catherine C. Marshall
FCCM
2002
IEEE
133views VLSI» more  FCCM 2002»
14 years 28 days ago
Reconfigurable Shape-Adaptive Template Matching Architectures
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...
Jörn Gause, Peter Y. K. Cheung, Wayne Luk
DAC
2008
ACM
14 years 9 months ago
Automated transistor sizing for FPGA architecture exploration
The creation of an FPGA requires extensive transistor-level design. This is necessary for both the final design, and during architecture exploration, when many different logic and...
Ian Kuon, Jonathan Rose
ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
14 years 2 months ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...