522 search results - page 97 / 105 » A Note on Designing Logical Circuits Using SAT |
DAC
2004
ACM
14 years 9 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...
FPGA
2000
ACM
13 years 11 months ago
2000
ACM
With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
SLIP
2003
ACM
14 years 1 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...