522 search results - page 98 / 105 » A Note on Designing Logical Circuits Using SAT |
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper introduces a method and tool-support for the automatic analysis and verification of hybrid and embedded control systems, whose continuous dynamics are often modelled u...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
The ability to guarantee the functional correctness of digital integrated circuits and, in particular, complex microprocessors, is a key task in the production of secure and trust...
CF
2006
ACM
14 years 1 months ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...