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» A Novel Approach for Hardware Based Sound Classification
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ICCD
2006
IEEE
182views Hardware» more  ICCD 2006»
16 years 26 days ago
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessab...
ISCA
2006
IEEE
142views Hardware» more  ISCA 2006»
15 years 10 months ago
Bulk Disambiguation of Speculative Threads in Multiprocessors
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
Luis Ceze, James Tuck, Josep Torrellas, Calin Casc...
MICRO
1994
IEEE
85views Hardware» more  MICRO 1994»
15 years 8 months ago
A high-performance microarchitecture with hardware-programmable functional units
This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Throu...
Rahul Razdan, Michael D. Smith
DSD
2010
IEEE
144views Hardware» more  DSD 2010»
15 years 4 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
ECCV
2006
Springer
16 years 5 months ago
Sampling Representative Examples for Dimensionality Reduction and Recognition - Bootstrap Bumping LDA
Abstract. We present a novel method for dimensionality reduction and recognition based on Linear Discriminant Analysis (LDA), which specifically deals with the Small Sample Size (S...
Hui Gao, James W. Davis