590 search results - page 11 / 118 » A Novel Method to Improve the Test Efficiency of VLSI Tests |
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
We present a novel global routing and cross-point assignment methodology for sea-of-gates (SOG) designs. Using the proposed congestion driven spanning trees (CDST), and continuous...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
INTEGRATION
2006
13 years 7 months ago
2006
Improving testability during the early stages of high-level synthesis has several benefits including reduced test hardware overheads, reduced test costs, reduced design iterations...
RECOMB
2009
Springer
14 years 8 months ago
2009
Springer
The availability of high density single nucleotide polymorphisms (SNPs) data has made genome-wide association study computationally challenging. Twolocus epistasis (gene-gene inter...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...