590 search results - page 7 / 118 » A Novel Method to Improve the Test Efficiency of VLSI Tests |
APBC
2004
13 years 9 months ago
2004
This paper introduces a novel method for minimum number of gene (feature) selection for a classification problem based on gene expression data with an objective function to maximi...
ICCAD
1995
IEEE
13 years 11 months ago
1995
IEEE
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
GLVLSI
2009
IEEE
13 years 5 months ago
2009
IEEE
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
DFT
2000
IEEE
13 years 12 months ago
2000
IEEE
Because domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very popularly used to design highperformance processors. However: dom...
ET
2002
13 years 7 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...