130 search results - page 23 / 26 » A Novel Metric for Interconnect Architecture Performance |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Chips manufactured in 90 nm technology have shown large parametric variations, and a worsening trend is predicted. These parametric variations make circuit optimization difficult ...
DATE
2009
IEEE
14 years 1 months ago
2009
IEEE
—In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit...
CF
2004
ACM
14 years 13 days ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
ICDE
2008
IEEE
14 years 8 months ago
2008
IEEE
Scientific and intelligence applications have special data handling needs. In these settings, data does not fit the standard model of short coded records that had dominated the dat...