139 search results - page 21 / 28 » A Novel Universal Sequencer Hardware |
DATE
2003
IEEE
14 years 3 months ago
2003
IEEE
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation...
ICCAD
1998
IEEE
14 years 2 months ago
1998
IEEE
Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip...
ISCA
1998
IEEE
14 years 2 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
RV
2010
Springer
13 years 8 months ago
2010
Springer
Researchers have developed a number of runtime verification tools that generate runtime monitors in the form of AspectJ aspects. In this work, we present Clara, a novel framework ...
BMCBI
2008
13 years 10 months ago
2008
Background: Prediction of transmembrane (TM) helices by statistical methods suffers from lack of sufficient training data. Current best methods use hundreds or even thousands of f...