Sciweavers

471 search results - page 5 / 95
» A Parallel Hardware Architecture for Image Feature Detection
Sort
View
VISUALIZATION
2003
IEEE
14 years 22 days ago
Fast Volume Segmentation With Simultaneous Visualization Using Programmable Graphics Hardware
Segmentation of structures from measured volume data, such as anatomy in medical imaging, is a challenging data-dependent task. In this paper, we present a segmentation method tha...
Anthony Sherbondy, Michael Houston, Sandy Napel
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 1 months ago
An Organic Computing architecture for visual microprocessors based on Marching Pixels
—The paper presents architecture and synthesis results for an organic computing hardware for smart CMOS camera chips. The organic behavior in the chip hardware is based on distri...
Dietmar Fey, Marcus Komann, Frank Schurz, Andreas ...
ISCAS
2003
IEEE
144views Hardware» more  ISCAS 2003»
14 years 23 days ago
A flexible global readout architecture for an analogue SIMD vision chip
A new vision chip, SCAMP-2, has been developed in a 0.35µm CMOS technology. In this paper, the design of the chip is presented, with particular emphasis on its readout architectu...
Piotr Dudek
PPSN
2004
Springer
14 years 25 days ago
Recognizing Speed Limit Sign Numbers by Evolvable Hardware
An automatic traffic sign detection system would be important in a driver assistance system. In this paper, an approach for detecting numbers on speed limit signs is proposed. Suc...
Jim Torresen, Jorgen W. Bakke, Lukás Sekani...
ISVC
2005
Springer
14 years 29 days ago
Toward Real Time Fractal Image Compression Using Graphics Hardware
Abstract. In this paper, we present a parallel fractal image compression using the programmable graphics hardware. The main problem of fractal compression is the very high computin...
Ugo Erra