31 search results - page 4 / 7 » A Parallel and Modular Architecture for 802.16e LDPC Codes |
ASAP
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardw...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
Channel coding is an important building block in communication systems since it ensures the quality of service. Irregular repeat-accumulate (IRA) codes belong to the class of Low-...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
A new technique to acquire pseudo-noise (PN) sequences has been recently proposed in [1] and [2]. It is based on the paradigm of iterative Message Passing (iMP) to be run on loopy...